With a fab line yield of consistently 98-99 per cent and world-class levels of electrical wafer sort yield, we strive to meet our customers’ production needs for volume market delivery and the highest possible quality wafers.

Extending the close co-operation with the customers in the prototyping phase, our engineering team prepares the product for volume production. Corner lots or matrix lots are normally processed to determine the process fit and margins between the design and process. Yield roadmaps and yield improvement activities are systematically planned together with the customers to effectively bring the customer product to mass production. Such close cooperation and mutual learning help ensure that world-class yield levels are achieved quickly.

As an integral part of our yield improvement efforts, we are constantly monitoring and studying all possible methods to reduce the defect density for the wafer manufacturing processes. One approach is to implement best-known-methods from our motherfabs. Another is the continuous monitoring and feedback of defect levels from all fab processing tools.

To support yield and baseline defect density improvements, we are equipped with a full-scale Failure Analysis lab and an experienced team that provide extensive and advanced Failure Analysis services.

The chart below gives a brief overview of the whole process undertaken to ensure best-in-class D0 performances.